About Etched

Etched is building the world’s first AI inference chip purpose-built for transformers, delivering over 10x the performance of NVIDIA GPUs. But that’s just the beginning. Our broader vision is to completely rethink the chip development lifecycle for a post-Moore world—enabling faster, more efficient custom silicon development than ever before. Backed by hundreds of millions from top investors, our team includes industry legends like Brian Loiler (who built products driving 80% of NVIDIA’s revenue), David Munday (who built Google’s TPU v1–v5 software and firmware stack), Mark Ross (former Cypress CTO), and Ajat Hukkoo (renowned Broadcom and Intel design exec). Etched is redefining the infrastructure layer for the fastest growing industry in history.

About the Role
We’re looking for a Head of SoC Design to help lead front-end design efforts for one of the largest and most complex AI SoCs ever built. Reporting directly to the VP of Engineering, you’ll own roughly half of the design organization and play a foundational role in the execution of one of the largest and most complex AI chips ever built. This is a high-impact leadership role overseeing SoC RTL design for external IP and comms blocks as well as SoC integration—working closely with RTL, verification, PD, and architecture leads to drive our chip from spec to tape-out.

Key responsibilities

• Own SoC integration and front-end RTL design for all external IP, including comms protocols like PCIe, CXL, and Ethernet

• Lead a high-performing design team responsible for system-level RTL, subsystem integration, and third-party IP delivery

• Manage end-to-end external IP lifecycle: vendor selection, customization, integration, validation, and maintenance

• Partner with the Head of IP Design to jointly lead the broader design org, ensuring architectural alignment and delivery cadence

• Collaborate with physical design and architecture, floorplanning, and system connectivity

• Work closely with verification, firmware, and validation to ensure functional correctness, performance, and power targets

• Drive execution from architecture to tape-out, including milestone definition, cross-functional coordination, and risk management

• Establish and scale SoC design methodologies and best practices across a rapidly growing team

• Mentor and develop technical leaders while helping to recruit top-tier design talent

You may be a good fit if you have

• Deep experience in SoC and IP design, including 5+ years leading technical teams

• Deep knowledge of SoC integration, front-end RTL, and IP-based design at advanced process nodes

• Proven track record managing large-scale SoC execution from spec to tape-out

• Expertise in integrating comms and memory interfaces (e.g., PCIe, CXL, Ethernet, DDR, HBM)

• Experience working with third-party IP vendors and managing complex dependencies

• Strong collaboration skills across architecture, PD, verification, and systems

• Proficiency in SystemVerilog and scripting languages like Python or Tcl

Strong candidates may also have experience with

• High-speed interface protocols such as PCIe, CXL, and Ethernet.

• Memory technologies including DDR and HBM, and related memory controller architectures.

• Low-power design techniques and methodologies, including power gating and dynamic voltage scaling.

• Experience with performance and power modeling, including trade-off analysis for design optimization.

• Scripting and automation in Python, Perl, Tcl, and Shell to improve design efficiency and workflow automation.

• Experience with physical design challenges such as floorplanning, signal integrity, and timing closure.

Benefits

• Full medical, dental, and vision packages

• Housing subsidy of $2,000/month for those living within walking distance of the office

• Daily lunch and dinner in our office with a $70 meal stipend/day

• Relocation support for those moving to San Jose

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.